1. Field of the Invention
Embodiments of the present invention generally relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device and a method for manufacturing the same that prevents a short between a bit line contact plug and a storage node contact plug to improve characteristics of the semiconductor device.
2. Description of the Related Art
A semiconductor device can be operated depending on a designated object through processes of implanting impurities into a given region in a silicon wafer or depositing a new material. In order to perform the designated object, the semiconductor device comprises various elements such as a transistor, a capacitor and a resistor which are connected through a conductive layer in order to exchange data or signals.
As a manufacturing technique of the semiconductor device has been developed to improve integration of the semiconductor device, an effort of forming more chips in one wafer has been continued. As a result, the minimum width of the design rule has been smaller in order to increase the integration. Also, the semiconductor device has been required to operate at a faster speed and reduce power consumption.
In order to improve the integration, the size of components in the semiconductor device is required to be reduced, and the length and width of connection lines are required to be decreased. Lines used in a semiconductor memory device include a word line for transmitting control signals and a bit line for transmitting data. When the width or cross-section of the word line and the bit line are reduced, resistance that disturbs transmission of control signals or data increases. The increase of resistance delays the transmission speed of signals and data in the semiconductor device, increases power consumption and degrades operation stability of the semiconductor memory device.
In spite of increase of the integration, when the width of the word line and the bit line is maintained to prevent the increase of resistance like the prior art, a physical distance between adjacent word lines or bit lines cannot but become closer. In case of the bit line for transmitting data transmitted from a unit cell capacitor in comparison with the word line for transmitting control signals with a relatively high potential, data may not be normally transmitted by increase of parasite capacitance. When data are smoothly transmitted through the bit line, a sense amplifier for sensing and amplifying data cannot sense the data, which means that the semiconductor device cannot output data stored in a unit cell to the outside.
In order to prevent the increase of parasite capacitance of the bit line, the amount of electric charges corresponding to data outputted from the unit cell may be increased. The size of the capacitor in the unit cell of the semiconductor memory device is required to become larger so as to increase the amount of charges. However, as the integration of the semiconductor memory device increases, the area occupied by the capacitor of the semiconductor memory device is also reduced.
The reduction of the area occupied by the capacitor means the decrease of the size of the unit cell of the semiconductor device. For example, the size of the unit cell decreases from 8F2 to 6F2 and from 6F2 to 4F2. F means the minimum distance between fine patterns on the design rule. The reduction of the size of the unit cell may be understood as the decrease of the minimum distance between fine patterns on the design rule.
It means that the size of the unit cell of 8F2 is reduced by 2F2 in case of a semiconductor device having the unit cell of 6F2. As a result, in case of the semiconductor device having a unit cell of 8F2, an active region having an oval shape has a major axis is in parallel to that of a bit line, and a word line has a protruded structure toward a semiconductor substrate. However, in case of the semiconductor device having a unit cell of 6F2, an active region having an oval shape has a major axis tilted at a given angle with that of a bit line, and a word line has a buried-type gate buried in a semiconductor substrate.
In case of the semiconductor device having a unit cell of 6F2, a bit line contact plug is coupled with an active region between buried-type gates, and a bit line is coupled to the upper portion of the bit line contact plug. Also, a storage node contact plug is disposed at both sides of the bit line and connected to the active region.
However, the bit lines are mis-aligned so that the bit line is not connected to the center part of the bit line contact plug but to the end of the bit line contact plug. The bit line contact plug is connected to the storage node contact plug disposed at both side of the bit line, which results in a short.
In order to prevent the short between the bit line contact plug and the storage node contact plug, the width of the bit line is formed to be larger or the width of the spacer disposed at sidewalls of the bit lines is formed to be thicker. As a result, the contact area between the active region and the storage node contact plug is reduced, thereby increasing resistance.